Regviz

NXP Semiconductors /LPC5410x /GINT0 /PORT_ENA1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PORT_ENA1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC5410x/GINT0/PORT_ENA1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ENA

Description

GPIO grouped interrupt port 0 enable register

Fields

ENA

Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data